Instruction Generation for Hybrid Reconfigurable Systems

Regularity extraction attempts to find common sub-structures (templates) in one or a collection of circuits (graphs). There are many applications for regularity extraction, including, but not limited to, compiler instruction generation and selection for hybrid (re)configurable systems, scheduling during logic synthesis, system-level partitioning and FPGA mapping and placement. We aim to build a general profiling technique for simultaneous template generation and matching, which is applicable to any task that uses a directed labeled graph. We target the generation and matching algorithm towards instruction generation and selection, though the methods we present are general enough to be applied to any regularity extraction problem represented by a directed labeled graph.